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rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad603 * features linear in db gain control pin programmable gain ranges C11 db to +31 db with 90 mhz bandwidth 9 db to 51 db with 9 mhz bandwidth any intermediate range, e.g., C1 db to +41 db with 30 mhz bandwidth bandwidth independent of variable gain 1.3 nv/ hz input noise spectral density 0.5 db typical gain accuracy mil-std-883 compliant and desc versions available applications rf/if agc amplifier video gain control a/d range extension signal measurement low noise, 90 mhz variable-gain amplifier product description the ad603 is a low noise, voltage-controlled amplifier for use in rf and if agc systems. it provides accurate, pin selectable gains of ?1 db to +31 db with a bandwidth of 90 mhz or 9 db to 51 db with a bandwidth of 9 mhz. any intermediate gain range may be arranged using one external resistor. the input referred noise spectral density is only 1.3 nv/ hz and power con- sumption is 125 mw at the recommended 5 v supplies. the decibel gain is ?inear in db,?accurately calibrated, and stable over temperature and supply. the gain is controlled at a high impedance (50 m ? ), low bias (200 na) differential input; the scaling is 25 mv/db, requiring a gain-control voltage of only functional block diagram scaling reference v g gain control interface ad603 precision passive input attenuator fixed gain amplifier * normal values r = 2r ladder network vpos vneg gpos gneg vinp comm 0db ?.02db ?2.04db ?8.06db ?4.08db ?0.1db ?6.12db ?2.14db rrrrrrr 2r 2r 2r 2r 2r 2r r 20 * 694 * 6.44k * v out fdbk 1 v to span the central 40 db of the gain range. an over- and underrange of 1 db is provided whatever the selected range. the gain-control response time is less than 1 s for a 40 db change. the differential gain-control interface allows the use of either differential or single-ended positive or negative control voltages. several of these amplifiers may be cascaded and their gain- control gains offset to optimize the system s/n ratio. the ad603 can drive a load impedance as low as 100 ? with low distortion. for a 500 ? load in shunt with 5 pf, the total harmonic distortion for a 1 v sinusoidal output at 10 mhz is typically ?0 dbc. the peak specified output is 2.5 v mini- mum into a 500 ? load, or 1 v into a 100 ? load. the ad603 uses a proprietary circuit topology?he x-amp. the x-amp comprises a variable attenuator of 0 db to ?2.14 db followed by a fixed-gain amplifier. because of the atten uator, the amplifier never has to cope with l arge inputs and can use negative feedback to define its (fixed) gain and dynamic perfor- mance. the attenuator has an input resistance of 100 ? , laser trimmed to 3%, and comprises a seven-stage r-2r ladder net- work, resulting in an attenuation between tap points of 6.021 db. a proprietary interpolation technique provides a c ontinuous gain-control function which is linear in db. the ad603a is specified for operation from ?0 c to +85 c and is available in both 8-lead soic (r) and 8-lead ceramic dip (q). the ad603s is specified for operation from ?5 c to +125 c and is available in an 8-lead ceramic dip (q). the ad603 is also available under desc smd 5962-94572. * patented. x-amp is a trademark of analog devices, inc. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000
ad603?pecifications rev. d C2C model ad603 parameter conditions min typ max unit input characteristics input resistance pins 3 to 4 97 100 103 ? input capacitance 2pf input noise spectral density 1 input short circuited 1.3 nv/ hz noise figure f = 10 mhz, gain = max, r s = 10 ? 8.8 db 1 db compression point f = 10 mhz, gain = max, r s = 10 ? ?1 dbm peak input voltage 1.4 2v output characteristics ? db bandwidth v out = 100 mv rms 90 mhz slew rate r l 500 ? 275 v/ s peak output 2 r l 500 ? 2.5 3.0 v output impedance f 10 mhz 2 ? output short-circuit current 50 ma group delay change vs. gain f = 3 mhz; full gain range 2ns group delay change vs. frequency v g = 0 v; f = 1 mhz to 10 mhz 2ns differential gain 0.2 % differential phase 0.2 degree total harmonic distortion f = 10 mhz, v out = 1 v rms ?0 dbc 3rd order intercept f = 40 mhz, gain = max, r s = 50 ? 15 dbm accuracy gain accuracy ?00 mv v g +500 mv 0.5 1 db t min to t max 1.5 db output offset voltage 3 v g = 0 v 20 mv t min to t max 30 mv output offset variation vs. v g ?00 mv v g +500 mv 20 mv t min to t max 30 mv gain control interface gain scaling factor 39.4 40 40.6 db/v t min to t max 38 42 db/v gneg, gpos voltage range 4 ?.2 +2.0 v input bias current 200 na input offset current 10 na differential input resistance pins 1 to 2 50 m ? response rate full 40 db gain change 40 db/ s power supply specified operating range 4.75 6.3 v quiescent current 12.5 17 ma t min to t max 20 ma notes 1 typical open or short-circuited input; noise is lower when system is set to maximum gain and input is short-circuited. this fig ure includes the effects of both voltage and current noise sources. 2 using resistive loads of 500 ? or greater, or with the addition of a 1 k ? pull-down resistor when driving lower loads. 3 the dc gain of the main amplifier in the ad603 is 35.7; thus, an input offset of 100 v becomes a 3.57 mv output offset. 4 gneg and gpos, gain control, voltage range is guaranteed to be within the range of v s + 4.2 v to +v s ?3.4 v over the full temperature range of ?0 c to +85 c. specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality le vels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. specifications subject to change without notice. (@ t a = 25 c, v s = 5 v, ?00 mv v g +500 mv, gneg = 0 v, ?0 db to +30 db gain range, r l = 500 , and c l = 5 pf, unless otherwise noted.)
ad603 rev. d C3C absolute maximum ratings 1 supply voltage v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 v internal voltage vinp (pin 3) . . . . . . . . . . . 2 v continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s for 10 ms gpos, gneg (pins 1, 2) . . . . . . . . . . . . . . . . . . . . . . . v s internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . 400 mw operating temperature range ad603a . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 c to +85 c ad603s . . . . . . . . . . . . . . . . . . . . . . . . . . 55 c to +125 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 thermal characteristics: 8-lead soic package: ja = 155 c/w, jc = 33 c/w 8-lead ceramic package: ja = 140 c/w, jc = 15 c/w pin function descriptions pin mnemonic description 1 gpos gain-control input ?i (positive voltage increases gain) 2 gneg gain-control input ?o (negative voltage increases gain) 3 vinp amplifier input 4 comm amplifier ground 5 fdbk connection to feedback network 6 vneg negative supply input 7 vout amplifier output 8 vpos positive supply input connection diagrams 8-lead plastic soic (r) package 8-lead ceramic dip (q) package top view (not to scale) 8 7 6 5 1 2 3 4 gpos gneg vinp vpos vout vneg fdbk comm ad603 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad603 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recom- mended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide temperature package package part number range description option ad603ar 40 c to +85 c 8-lead soic so-8 ad603aq 40 c to +85 c 8-lead ceramic dip q-8 ad603sq/883b * ?5 c to +125 c 8-lead ceramic dip q-8 ad603-eb evaluation board ad603achips ?0 c to +85 c die ad603ar-reel ?0 c to +85 c 13" reel so-8 ad603ar-reel7 ?0 c to +85 c 7" reel so-8 * refer to ad603 military data sheet. also available as 5962-9457203mpa.
rev. d C4C ad603 theory of operation the ad603 comprises a fixed-gain amplifier, preceded by a broadband passive attenuator of 0 db to 42.14 db, having a gain-control scaling factor of 40 db per volt. the fixed gain is laser-trimmed in two ranges, to either 31.07 db ( 35.8) or 50 db ( 358), or may be set to any range in between using one external resistor between pins 5 and 7. somewhat higher gain can be obtained by connecting the resistor from pin 5 to common, but the increase in output offset voltage limits the maximum gain to about 60 db. for any given range, the bandwidth is independent of the voltage-controlled gain. this system provides an under- and overrange of 1.07 db in all cases; for example, the overall gain is ?1.07 db to 31.07 db in the maximum- bandwidth mode (pin 5 and pin 7 strapped). this x-amp structure has many advantages over former methods of gain-control based on nonlinear elements. most importantly, the fixed-gain amplifier can use negative feedback to increase its accuracy. since large inputs are first attenuated, the amplifier input is always small. for example, to deliver a 1 v output in the ? db/+41 db mode (that is, using a fixed amplifier gain of 41.07 db) its input is only 8.84 mv; thus the distortion can be very low. equally important, the small-signal gain and phase response, and thus the pulse response, are essentially indepen- dent of gain. figure 1 is a simplified schematic. the input attenuator is a seven-section r-2r ladder network, using untrimmed resistors of nominally r = 62.5 ? , which results in a characteristic resis- tance of 125 ? 20%. a shunt resistor is included at the input and laser trimmed to establish a more exact input resistance of 100 ? 3%, which ensures accurate operation (gain and hp corner frequency) when used in conjunction with external res istors or capacitors. the nominal maximum signal at input vinp is 1 v rms ( 1.4 v peak) when using the recommended 5 v supplies, alt hough operation to 2 v peak is permissible with some increase in hf distortion and feedthrough. pin 4 (signal common) must be connected directly to the input ground; significant impedance in this connection will reduce the gain accuracy. the signal applied at the input of the ladder network is attenu- ated by 6.02 db by each section; thus, the attenuation to each of the taps is progressively 0 db, 6.02 db, 12.04 db, 18.06 db, 24.08 db, 30.1 db, 36.12 db and 42.14 db. a unique circuit technique is employed to interpolate between these tap-points, indicated by the ?lider?in figure 1, thus providing continuous attenuation from 0 db to 42.14 db. it will help, in understanding the ad603, to think in terms of a mechanical means for moving this slider from left to right; in fact, its ?osition?is controlled by the voltage between pins 1 and 2. the details of the gain- control interface are discussed later. the gain is at all times very exactly determined, and a linear -in-db relationship is automatically guaranteed by the exponen tial nature of the attenuation in the ladder network (the x-amp principle). in practice, the gain deviates slightly from the ideal law, by about 0.2 db peak (see, for example, figure 16). noise performance an important advantage of the x-amp is its superior noise per- formance. the nominal resistance seen at inner tap points is 41.7 ? (one third of 125 ? ), which exhibits a johnson noise- spectral density (nsd) of 0.83 nv/ hz (that is, 4ktr ) at 27 c, which is a large fraction of the total input noise. the first stage of the amplifier contributes a further 1 nv/ hz , for a total input noise of 1.3 nv/ hz . it will be apparent that it is essential to use a low resistance in the ladder network to achieve the very low specified noise level. the signal? source impedance forms a voltage divider with the ad603? 100 ? input resistance. in some applications, the resulting attenuation may be unaccept- able, requiring the use of an external buffer or preamplifier to match a high impedance source to the low impedance ad603. the noise at maximum gain (that is, at the 0 db tap) depends on whether the input is short-circuited or open-circuited: when shorted, the minimum nsd of slightly over 1 nv/ hz is achieved; when open, the resistance of 100 ? looking into the first tap generates 1.29 nv/ hz , so the noise increases to a total of 1.63 nv/ hz . (this last calculation would be important if the ad603 were preceded by, for example, a 900 ? resistor to allow operation from inputs up to 10 v rms.) as the selected tap moves away from the input, the dependence of the noise on source impedance quickly diminishes. apart from the small variations just discussed, the signal-to- noise (s/n) ratio at the output is essentially independent of the attenuator setting. for example, on the ?1 db/+31 db range the fixed gain of 35.8 raises the output nsd to 46.5 nv/ hz . thus, for the maximum undistorted output of 1 v rms and a 1 mhz bandwidth, the output s/n ratio would be 86.6 db, that is, 20 log (1 v/46.5 v). scaling reference v g gain control interface ad603 precision passive input attenuator fixed gain amplifier * normal values r = 2r ladder network vpos vneg gpos gneg vinp comm 0db 6.02db 12.04db 18.06db 24.08db 30.1db 36.12db 42.14db rrrrrrr 2r 2r 2r 2r 2r 2r r 20 * 694 * 6.44k * v out fdbk figure 1. simplified block diagram of the ad603 * patented. x-amp is a trademark of analog devices, inc.
ad603 rev. d C5C the gain-control interface the attenuation is controlled through a differential, high- impedance (50 m ? ) input, with a scaling factor which is laser- trimmed to 40 db per volt, that is, 25 mv/db. an internal bandgap reference ensures stability of the scaling with respect to supply and temperature variations. when the differential input voltage v g = 0 v, the attenuator ?lider?is centered, providing an attenuation of 21.07 db. for the maximum bandwidth range, this results in an overall gain of 10 db (= ?1.07 db + 31.07 db). when the control input is ?00 mv, the gain is lowered by 20 db (= 0.500 v 40 db/v), to ?0 db; when set to +500 mv, the gain is increased by 20 db, to 30 db. when this interface is overdriven in either direction, the gain approaches either ?1.07 db (= 42.14 db + 31.07 db) or 31.07 db (= 0 + 31.07 db), respectively. the only constraint on the gain-control voltage is that it be kept within the common-mode range (?.2 v to + 2.0 v assuming +5 v supplies) of the gain control interface. the basic gain of the ad603 can thus be calculated using the following simple expression: gain (db) = 40 v g + 10 (1) where v g is in volts. when pins 5 and 7 are strapped (see next section) the gain becomes gain (db) = 40 v g + 20 for 0 to +40 db and gain (db) = 40 v g + 30 for +10 to +50 db (2) the high impedance gain-control input ensures minimal loading when driving many amplifiers in multiple channel or cascaded applications. the differential capability provides flexibility in choosing the appropriate signal levels and polarities for various control schemes. for example, if the gain is to be controlled by a dac providing a posi tive only ground-referenced outp ut, the ?ain control lo?(gneg) pin should be biased to a fixed offset of 500 mv, to set the gain to ?0 db when ?ain control hi?(gpos) is at zero, and to 30 db when at 1.00 v. it is a simple matter to include a voltage divider to achieve other scaling factors. when using an 8-bit dac having an fs output of 2.55 v (10 mv/bit), a divider ratio of 2 (generating 5 mv/bit) would result in a gain-setting resolution of 0.2 db/bit. the use of such offsets is valuable when two ad603s are cascaded, when various options exist for optimizing the s/n profile, as will be shown later. programming the fixed-gain amplifier using pin strapping access to the feedback network is provided at pin 5 (fdbk). the user may program the gain of the ad603? output amplifier using this pin, as shown in figure 2. there are three modes: in the default mode, fdbk is unconnected, providing the range +9 db/+51 db; when v out and fdbk are shorted, the gain is lowered to ?1 db/+31 db; when an external resistor is placed between v out and fdbk any intermediate gain can be achieved, for example, ? db/+41 db. figure 3 shows the nominal maxi- mum gain versus external resistor for this mode. gpos gneg vinp comm vpos v out vneg fdbk ad603 vc1 vc2 v in vpos v out vneg a. C10 db to +30 db; 90 mhz bandwidth gpos gneg vinp comm vpos v out vneg fdbk ad603 vc1 vc2 v in vpos v out vneg 2.15k 5.6pf b. 0 db to +40 db; 30 mhz bandwidth gpos gneg vinp comm vpos v out vneg fdbk ad603 vc1 vc2 v in vpos v out vneg 18pf c. 10 db to 50 db; 9 mhz bandwidth figure 2. pin strapping to set gain r ext 52 10 1m decibels 100 1k 10k 100k 50 48 46 44 42 40 38 36 34 32 30 1:vdb (out) 2:vdb (out) vdb (out) figure 3. gain vs. r ext , showing worst-case limits assuming internal resistors have a maximum tolerance of 20%
rev. d C6C ad603 optionally, when a resistor is placed from fdbk to comm, higher gains can be achieved. this fourth mode is of limited value because of the low bandwidth and the elevated output off- sets; it is thus not included in figure 2. the gain of this amplifier in the first two modes is set by the ratio of on-chip laser-trimmed resistors. while the ratio of these resist ors is very accurate, the absolute value of these resi stors can vary by as much as 20%. thus, when an external resistor is connected in parallel with the nominal 6.44 k ? 20% inter- nal resistor, the overall gain accuracy is somewhat poorer. the worst-case error occurs at about 2 k ? (see figure 4). r ext 1.2 10 1m decibels 100 1k 10k 100k 1.0 0.8 0.6 0.4 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1:vdb (out) ( 1):vdb (o ref ) vdb (out) vdb (o ref ) figure 4. worst-case gain error, assuming internal resis- tors have a maximum tolerance of C20% (top curve) or +20% (bottom curve) while the gain-bandwidth product of the fixed-gain amplifier is about 4 ghz, the actual bandwidth is not exactly related to the maximum gain. this is because there is a slight enhancing of the ac response magnitude on the maximum bandwidth range, due to higher order poles in the open-loop gain function; this mild peaking is not present on the higher gain ranges. figure 2 shows how optional capacitors may be added to extend the frequency response in high gain modes. cascading two ad603s two or more ad603s can be connected in series to achieve higher gain. invariably, ac coupling must be used to prevent the dc offset voltage at the output of each amp lifier from overload- ing the following amplifier at maximum gain. the required high pass coupling network will usually be just a capacitor, chosen to set the desired corner frequency in conjunction with the well- defined 100 ? input resistance of the following amplifier. for two ad603s, the total gain-control range becomes 84 db (two times 42.14 db); the overall ? db bandwidth of cascaded stages will be somewhat reduced. depending on the pin-strapping, the gain and bandwidth for two cascaded amplifiers can range from ?2 db to +62 db (with a bandwidth of about 70 mhz) to +22 db to +102 db (with a bandwidth of about 6 mhz). there are several ways of connecting the gain-control inputs in cascaded operation. the choice depends on whether it is impor- tant to achieve the highest possible instantaneous signal-to-noise ratio (isnr), or, alternatively, to minimize the ripple in the gain error. the following examples feature the ad603 programmed for maximum bandwidth; the explanations apply to other gain/ bandwidth combinations with appropriate changes to the arrange- ments for setting the maximum gain. sequential mode (optimal s/n ratio) in the sequential mode of operation, the isnr is maintained at its highest level for as much of the gain control range possible. figure 5 shows the snr over a gain range of ?2 db to +62 db, assuming an output of 1 v rms and a 1 mhz bandwidth; figure 6 shows the general connections to accomplish this. here, both the positive gain-control inputs (gpos) are driven in parallel by a positive-only, ground-referenced source with a range of 0 v to +2 v, while the negative gain-control inputs (gneg) arc biased by stable voltages to provide the needed gain-offsets. these volt- ages may be provided by resistive dividers operating from a common voltage reference. v c 90 s/n ratio db 0.2 2.2 0.2 0.6 1.0 1.4 1.8 85 80 75 70 65 60 55 50 figure 5. snr vs. control voltagesequential control (1 mhz bandwidth) the gains are offset (figure 7) such that a2? gain is increased only after a1? gain has reached its maximum value. note that for a differential input of ?00 mv or less, the gain of a single amplifier (a1 or a2) will be at its minimum value of ?1.07 db; for a differential input of +600 mv or more, the gain will be at its maximum value of 31.07 db. control inputs beyond these limits will not affect the gain and can be tolerated without dam- age or foldover in the response. this is an important aspect of the ad603? gain-control response. (see the specifications sec- tion of this data sheet for more details on the allowable voltage range) the gain is now gain (db) = 40 v g + g o (3) where v g is the applied control voltage and g o is determined by the gain range chosen. in the e xplanatory notes that follow, we assume the maximum-bandwidth connections are us ed, for which g o is ?0 db.
ad603 rev. d C7C 31.07db 42.14db gpos gneg 31.07db 42.14db gpos gneg 40.00db 51.07db 8.93db input 0db v c = 0v a1 a2 v g1 v g2 v o1 = 0.473v v o2 = 1.526v output 20db a. 31.07db 42.14db gpos gneg 31.07db 0db gpos gneg 0db 11.07db 31.07db input 0db v c = 1.0v v g1 v g2 v o1 = 0.473v v o2 = 1.526v output 20db b. 31.07db 2.14db gpos gneg 31.07db 0db gpos gneg 0db 28.93db 31.07db input 0db v c = 2.0v v g1 v g2 v o1 = 0.473v v o2 = 1.526v output 60db c. figure 6. ad603 gain control input calculations for sequential control operation +31.07db +10db a1 a2 +31.07db +28.96db 11.07db 11.07db 0.473 1.526 8.93db * * 0 0.5 1.0 1.50 2.0 v c (v) 20 0 20 40 60 62.14 22.14 gain (db) * gain offset of 1.07db, or 26.75mv figure 7. explanation of offset calibration for sequential control with reference to figure 6, note that v g1 refers to the differen- tial gain-control input to a1 and v g2 refers to the differential gain-control input to a2. when v g is zero, v g1 = ?73 mv and thus the gain of a1 is ?.93 db (recall that the gain of each indi- vidual amplifier in the maximum-bandwidth mode is ?0 db for v g = ?00 mv and 10 db for v g = 0 v); meanwhile, v g2 = ?.908 v so the gain of a2 is ?inned?at ?1.07 db. the over- all gain is thus ?0 db. this situation is shown in figure 6a. when v g = +1.00 v, v g1 = 1.00 v ?0.473 v = +0.526 v, which sets the gain of a1 to at nearly its maximum value of 31.07 db, while v g2 = 1.00 v ?1.526 v = 0.526 v, which sets a2? gain at nearly its minimum value ?1.07 db. close analysis shows that the degree to which neither ad603 is completely pushed to its maximum or minimum gain exactly cancels in the overall gain, which is now +20 db. this is depicted in figure 6b. when v g = +2.0 v, the gain of a1 is pinned at 3 1.07 db and that of a2 is near its maximum value of 28.93 db, resulting in an overall gain of 60 db (see figure 6c). this mode of operation is further clarified by figure 8, which is a plot of the separate gains of a1 and a2 and the overall gain versus the control voltage. figure 9 is a plot of the gain error of the cascaded amplifiers versus the control voltage. figure 10 is a plot of the gain error of the cascaded stages versus the control voltages. v c 70 30 0.2 2.2 0.2 overall gain db 0.6 0.1 1.4 1.8 60 30 0 10 20 50 40 20 10 combined a1 a2 figure 8. plot of separate and overall gains in sequential control
rev. d C8C ad603 v c 90 10 s/n ratio db 80 50 40 30 20 70 60 0.2 2.2 0.2 0.6 1.0 1.4 1.8 figure 9. snr for cascaded stagessequential control v c 2.0 0.5 2.0 0.2 gain error db 1.5 0.0 1.0 1.5 1.0 0.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 figure 10. gain error for cascaded stagessequential control parallel mode (simplest gain-control interface) in this mode, the gain-control of voltage is applied to both inputs in parallel?he gpos pins of both a1 and a2 are con nected to the control voltage and the gnew inputs are grounded. the gain scaling is then doubled to 80 db/v, requiring only a 1.00 v change for an 80 db change of gain: gain (db) = 80 v g + g o (4) where, as before g o depends on the range selected; for example, in the maximum-bandwidth mode, g o is +20 db. alternatively, the gneg pins may be connected to an offset voltage of 0.500 v, in w hich case, g o is ?0 db. the amplitude of the gain ripple in this case is also doubled, as shown in f igure 11, while the instantane ous signal-to-noise ratio at the output of a2 now decreases linearly as the gain increased (figure 12). v c 2.0 0.5 2.0 0.2 gain error db 1.5 0.0 1.0 1.5 1.0 0.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 figure 11. gain error for cascaded stagesCparallel control v c 0.2 90 is/n ratio db 85 80 75 70 65 60 55 50 0 0.2 0.4 0.6 0.8 1.0 1.2 figure 12. isnr for cascaded stagesCparallel control low gain ripple mode (minimum gain error) as can be seen from figures 9 and 10, the error in the gain is periodic, that is, it shows a small ripple. (note that there is also a variation in the output offset voltage, which is due to the gain interpolation, but this is not exact in amplitude.) by offsetting the gains of a1 and a2 by half the period of the ripple, that is, by 3 db, the residual gain errors of the two amplifiers can be made to cancel. figure 13 shows that much lower gain ripple when configured in this manner. figure 14 plots the isnr as a function of gain; it is very similar to that in the ?arallel mode.
ad603 rev. d C9C v c 3.0 0.1 gain error db 2.5 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 figure 13. gain error for cascaded stagesClow ripple mode v c 0.2 90 is/n ratio db 85 80 75 70 65 60 55 50 0 0.2 0.4 0.6 0.8 1.0 1.2 figure 14. isnr vs. control voltageClow ripple mode theory of the ad603 a low noise agc amplifier figure 15 shows the ease with which the ad603 can be connected as an agc amplifier. the circuit illustrates many of the points previously discussed: it uses few parts, has linear-in-db gain, operates from a single supply, uses two cascaded amplifiers in sequential gain mode for maximum s/n ratio, and an external resistor programs each amplifier? gain. it also uses a simple temperature-compensated detector. the circuit operates from a single 10 v supply. resistors r1, r2, r3, and r4 bias the common pins of a1 and a2 at 5 v. this pin is a low impedance point and must have a low impedance path to ground, here provided by the 100 f tantalum capacitors and the 0.1 f ceramic capacitors. the cascaded amplifiers operate in sequential gain. here, the offset voltage between the pins 2 (gneg) of a1 and a2 is 1.05 v (42.14 db 25 mv/db), provided by a voltage divider consisting of resistors r5, r6, and r7. using standard values, the offset is not exact, but it is not critical for this application. the gain of both a1 and a2 is programmed by resistors r13 and r14, respectively, to be about 42 db; thus the maximum gain of the circuit is twice that, or 84 db. the gain-control range can be shifted up by as much as 20 db by appropriate choices of r13 and r14. the circuit operates as follows. a1 and a2 are cascaded. capacitor c1 and the 100 ? of resistance at the input of a1 form a time- constant of 10 s. c2 blocks the small dc offset voltage at the output of a1 (which might otherwise saturate a2 at its maxi- mum gain) and introduces a high-pass corner at about 16 khz, eliminating low frequency noise. a half-wave detector is used, based on q1 and r8. the current into ca pacitor c av is just the difference between the colle ctor current of q2 (biased to be 300 a at 300 k, 27 c) and the col- lector current of q1, which increases with the amplitude of the a2 ad603 10v c8 0.1 f c2 0.1 f r14 2.49k 10v + r4 2.49k c6 0.1 f c5 100 f 2 r3 2.49k a1 ad603 10v c7 0.1 f c1 0.1 f r13 2.49k 10v + r2 2.49k c4 0.1 f c3 100 f 2 r1 2.49k rt 100 1 j1 r7 3.48k r6 1.05k r5 5.49k 1v offset for sequential gain 5.5v 6.5v notes 1 r t provides a 50 input impedance 2 c3 and c5 are tantalum 10v agc line c av 0.1 f this capacitor sets agc time constant v agc r9 1.54k r8 806 q1 2n3904 q2 2n3906 r10 1.24k r11 3.83k 5v r12 4.99k c11 0.1 f c9 0.1 f 10v j2 c10 0.1 f figure 15. a low noise agc amplifier
rev. d C10C ad603 output signal. the automatic gain control voltage, v agc , is the time-integral of this error current. in order for v agc (and thus the gain) to remain insensitive to short-term amplitude fluctuations in the output signal, the rectified current in q1 must, on average, exactly balance the current in q2. if the output of a2 is too small to do this, v agc will increase, causing the gain to increase, until q1 conducts sufficiently. consider the case where r8 is zero and the output voltage v out is a square wave at, say, 455 khz, which is well above the corner frequency of the control loop. during the time v out is negative with respect to the base voltage of q1, q1 conducts; when v out is positive, it is cut off. since the average collector current of q1 is forced to be 300 a, and the square wave has a duty-cycle of 1:1, q1? collector current when conducting must be 600 a. with r8 omitted, the peak amplitude of v out is forced to be just the v be of q1 at 600 a, typically about 700 mv, or 2 v be peak-to-peak. this voltage, hence the amplitude at which the output stabilizes, has a strong negative temperature coefficient (tc), typically ?.7 mv/ c. although this may not be troublesome in some applications, the correct value of r8 will render the output stable with temperature. to understand this, first note that the current in q2 is made to be proportional to absolute temperature (ptat). for the moment, continue to assume that the signal is a square wave. when q1 is conducting, v out is now the sum of v be and a voltage that is ptat and which can be chosen to have an equal but opposite tc to that of the v be . this is actually nothing more than an application of the ?andgap vol tage reference?principle. when r8 is chosen such that the sum of the voltage across it and the v be of q1 is close to the bandgap voltage of about 1.2 v, v out will be stable o ver a wide range of tempe ratures, provided, of course, that q1 and q2 share the same thermal environment. since the average emitter current is 600 a during each half- cycle of the square wave a resistor of 833 ? would add a ptat voltage of 500 mv at 300 k, increasing by 1.66 mv/ c. in prac- tice, the optimum value will depend on the type of transistor used and, to a lesser extent, on the waveform for which the temperature stability is to be optimized; for the inexpensive 2n3904/2n3906 pair and sine wave signals, the recommended value is 806 ? . this resistor also serves to lower the peak current in q1 when more typical signals (usually, sinusoidal) are involved, and the 1.8 khz lp filter it forms with c av helps to minimize distortion due to ripple in v agc . note that the output amplitude under sine wave conditions will be higher than for a square wave, since the average value of the current for an ideal rectifier would be 0.637 times as large, causing the output amplitude to be 1.88 (= 1.2/0.637) v, or 1.33 v rms. in practice, the somewhat nonideal rectifier results in the sine wave output being regulated to about 1.4 v rms, or 3.6 v p-p. the bandwidth of the circuit exceeds 40 mhz. at 10.7 mhz, the agc threshold is 100 v (?7 dbm) and its maximum gain is 83 db (20 log 1.4 v/100 v). the circuit holds its output at 1.4 v rms for inputs as low as ?7 dbm to +15 dbm (82 db), where the input signal exceeds the ad603? maximum input rating. for a 30 dbm input at 10.7 mhz, the second harmonic is 34 db down from the fundamental and the third harmonic is 35 db down. caution careful component selection, circuit layout, power-supply decoupling, and shielding are needed to minimize the ad603? susceptibility to interference from radio and tv stations, etc. in bench evaluation, we recommend placing all of the components in a shielded box and using feedthrough decoupling networks for the supply voltage. circuit layout and construction are also critical, since stray capacitances and lead inductances can form resonant circuits and are a potential source of circuit peaking, oscillation, or both.
ad603 rev. d C11C gain voltage volts gain error db 2.50 0.5 2.00 1.50 1.00 0.50 0.00 0.50 1.00 1.50 0.4 0.3 0.2 0.1 0.0 0.2 0.3 0.4 0.5 0.6 45mhz 70mhz 10.7mhz 455khz 70mhz figure 16. gain error vs. gain control voltage at 455 khz, 10.7 mhz, 45 mhz, 70 mhz frequency hz gain db 100k 1m 10m 100m ref level /div marker 505 156.739hz 31.550db 1.000db mag (udf) 35.509db 0.0deg 45.000deg marker 505 156.739hz phase (udf) 1.150deg figure 19. frequency and phase response vs. gain (gain = +30 db, p in = C30 dbm, pin 5 connected to pin 7) 10db/div figure 22. third order intermodula- tion distortion at 455 khz (10 probe used to hp3585a spectrum analyzer, gain = 0 db, p in = 0 dbm, pin 5 con- nected to pin 7) frequency hz gain db 100k 1m 10m 100m ref level /div marker 505 156.739hz 8.100db 1.000db mag (udf) 4.127db 0.0deg 45.000deg marker 505 156.739hz phase (udf) 1.338deg figure 17. frequency and phase response vs. gain (gain = C10 db, p in = C30 dbm, pin 5 connected to pin 7) gain control voltage volts group delay ns 7.60 0.6 7.40 7.20 7.00 6.80 6.60 6.40 0.4 0.2 0 0.2 0.4 0.6 figure 20. group delay vs. gain control voltage 10db/div &
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',a 12=', probe used to hp3585a spectrum analyzer, gain = 0 db, p in = 0 dbm, pin 5 con- nected to pin 7) frequency hz gain db 100k 1m 10m 100m ref level /div marker 505 156.739hz 11.850db 1.000db mag (udf) 15.859db 0.0deg 45.000deg marker 505 156.739hz phase (udf) 1.378deg figure 18. frequency and phase response vs. gain (gain = +10 db, p in = C30 dbm, pin 5 connected to pin 7) datel dvc 8500 hp3326a dual channel synthesizer 100 +5v 0.1 f 5v 511 ad603 10 probe hp3585a spectrum analyzer 0.1 f figure 21. third order intermodula- tion distortion test setup load resistance negative output voltage limit volts 1.0 0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 50 100 200 500 1000 2000 3.2 3.4 figure 24. typical output voltage swing vs. load resistance (negative output swing limits first)
rev. d C12C ad603 frequency hz input impedance 100k 102 100 98 96 1m 10m 100m 94 figure 25. input impedance vs. frequency (gain = C10 db) 1v 200ns 1v 100 90 10 0% figure 28. gain-control channel response time 3.5v 500mv 1.5v 44ns 50ns 456ns gnd gnd input 500mv/div output 500mv/div figure 31. transient response, g = 0 db, pin 5 connected to pin 7 (input is 500 ns period, 50% duty- cycle square wave, output is captured using tektronix 11402 digitizing oscilloscope) frequency hz input impedance 100k 102 100 98 96 1m 10m 100m 94 figure 26. input impedance vs. frequency (gain = +10 db) 4.5v 500mv 500mv 49ns 50ns 451ns input gnd 1v/div output gnd 500mv/div figure 29. input stage overload recovery time, pin 5 connected to pin 7 (input is 500 ns period, 50% duty-cycle square wave, output is captured using tektronix 11402 digitizing oscilloscope) 3.5v 500mv 1.5v 44ns 50ns 456ns input gnd 100mv/div output gnd 500mv/div figure 32. transient response, g = +20 db, pin 5 connected to pin 7 (input is 500 ns period, 50% duty- cycle square wave, output is captured using tektronix 11402 digitizing oscilloscope) frequency hz input impedance 100k 102 100 98 96 1m 10m 100m 94 &
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@=4d.$, )> 8v 1v 2v 49ns 50ns 451ns input gnd 100mv/div output gnd 1v/div figure 30. output stage overload recovery time, pin 5 connected to pin 7 (input is 500 ns period, 50% duty-cycle square wave, output is captured using tektronix 11402 digitizing oscilloscope) frequency hz psrr db 100k 0 20 40 60 1m 10m 100m 10 30 50 figure 33. psrr vs. frequency (worst case is negative supply psrr, shown here)
ad603 rev. d C13C figure 34. test setup used for: noise figure, 3rd order intercept and 1 db compression point measurements input frequency mhz input level dbm 10 0 5 10 25 15 20 30 50 70 t a = 25 c test setup figure 34 figure 37. 1 db compression point, C10 db/+30 db mode, gain = 30 db gain db noise figure db 23 20 21 19 17 15 13 5 11 9 7 21 22 23 24 25 26 27 28 29 30 t a = 25 c r s = 50 test setup figure 34 70mhz 30mhz 50mhz 10mhz figure 35. noise figure in C10 db/ +30 db mode input level dbm output level dbm 20 20 18 16 8 14 12 10 0 t a = 25 c test setup figure 34 10 30mhz 40mhz 70mhz figure 38. 3rd order intercept C10 db/ +30 db mode, gain = 10 db gain db noise figure db 30 21 19 17 15 13 5 11 9 7 31 32 33 34 35 36 37 38 39 40 t a = 25 c r s = 50 test setup figure 34 20mhz 10mhz figure 36. noise figure in 0 db/40 db mode input level dbm output level dbm 40 20 18 16 8 14 12 30 20 t a = 25 c r s = 50 r in = 50 r l = 100 test setup figure 34 10 30mhz 40mhz 70mhz figure 39. 3rd order interc ept, C10 db/ +30 db mode, gain = 30 db hp3326a dual channel synthesizer 100 +5v 0.1 f 5v 50 ad603 hp3585a spectrum analyzer datel dvc 8500 0.1 f
rev. d C14C ad603 outline dimensions dimensions shown in inches and (mm). 8-lead cerdip (q-8) 8 1 4 5 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.055 (1.4) max seating plane 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 0.405 (10.29) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 8-lead soic (so-8) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 85 4 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) c00539aC0C11/00 (rev. d) printed in u.s.a.

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